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M.Tech Very Large Scale Integration (VLSI)

M.Tech Very Large Scale Integration (VLSI)

M.Tech (Very Large Scale Integration)

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Your Program

M.Tech (Very Large Scale Integration)

Duration
ELIGIBILITY
ADMISSION PROCESS
FEES
2 Years (M.Tech. VLSI Engg) 60% in B. Tech / M.Sc. (Elex.) On the basis of performance in the online Multiple-Choice Question (MCQ) Test of 2 hours duration and personal interview. Rs. 1,20,000 per annum

About the Program

The M.Tech. (Very Large Scale Integration) Program of Suresh Gyan Vihar University, Jaipur is designed keeping in view the latest trends in the field of embedded system and circuit design. The students are given an overview of the various subjects of all the two disciplines during the tenure of their program. The various papers that are put to study during the program include the study of MOS VLSI, Computer aided VLSI design, analogy ICs and synthesis of digital system and MEMS in details. Therefore after completion of the program, the students are well versed with the entire area of all the two disciplines and their application in the current scenario.

Job Prospects

  • ASIC frontend designer
  • FPGA frontend designer
  • ASIC physical design engineer
  • EDA tool validation engineer
  • IP verification engineer
  • Board validation engineer

Program Structure

Semester 1

University Core

  • Technical Writing
  • Foundation Course – I
  • Proficiency in co-curricular activities

Program Core

  • MOS VLSI
  • VLSI Technology
  • System level design and Modelling of digital Systems
  • Digital system Design Lab
  • Embedded system and circuit design Lab
  • Review Seminar-I

Program Elective

  • Advanced computer Communication
  • Real Time
  • Memory design and testing
  • Testing And Fault Tolerance

Semester 2

University Core

  • Employability Skills VIII
  • Foundation Course –II
  • Proficiency in co-curricular activities

University Elective

  • Optimization technique
  • Statistical modeling

Program Core

  • Computer-Aided VLSI Design Advanced Digital Signal Processing
  • Analog ICs
  • Advanced Digital Signal Processing
  • Modeling and Simulation Lab
  • Review Seminar- II

Program Elective

  • Synthesis of Digital System Biomedical Instrumentation
  • Issues in Deep Sub-micron CMOS IC Design
  • Digital Image Processing
  • Advanced IC Technology

Semester 3

University Core

  • Employability Skills II
  • Pre Dissertation/Minor Project
  • Proficiency in co-curricular activities

University Elective

  • Research methodology
  • Estimation Theory

Program Core

  • Embedded System Design
  • VLSI Design Lab
  • Pre-Dissertation/ Minor Project M Tech Seminar
  • Industrial Project & Training

Program Elective

  • Reconfigurable Computing
  • Combinatorial Optimization Soft Skills
  • Micro-Electro-Mechanical-Systems
  • Microelectronics

Semester 4

Program Core

  • M. Tech. Dissertation / Thesis

Teaching

The typical percentage of time spent in different learning activities for this program is based on student choices. This information is collated from the previous year and will not be available if the program is new.

Year 1

Lecture, Seminar and Similar
90%
Independent Studies
10%

Year 2

Lecture, Seminar and Similar
80%
Independent Studies
20%

Assessment

Typically how work is assessed for this program is based on student choices. This information is collated from the previous year and will not be available if the program is new.

Year 1

Written Exams
60%
Practical Exams
40%

Year 2

Written Exams
60%
Practical Exams
40%
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