\nThis paper presents the design of programmable digital filter for transreceiver circuits. The designed filter
\ncovers a wide range of 10 MHz \u2013 40 MHz which covers a variety of digital wireless applications. The wide
\nbandwidth covers multiple wireless standards from TETRA, IS-95, GSM to TACS.
\nKeywords<\/strong>: Digital, filter, wireless<\/p>\n
INTRODUCTION<\/strong> The digital filters play a very important role in\u00a0almost every digital transmission technology. So\u00a0various researches has been done in this regard.\u00a0Digital filters are an essential elements of\u00a0transceivers especially with the coming in of\u00a0software defined radios and cognitive radios where\u00a0the digital circuitry of the radio needs to configure\u00a0the filters on the fly. A digital filter system usually\u00a0consists of an analog – to-digital converter to\u00a0sample the input signal which is followed by a\u00a0microprocessor and some peripheral components\u00a0such as memory to store data and filter coefficients\u00a0and finally a digital-to-analog converter completes\u00a0the output stage. The microprocessor implements\u00a0the digital filter by performing the necessary\u00a0mathematical operations by program instructions.\u00a0In some high performance applications, an FPGA\u00a0or ASIC or a specialized DSP is used instead of a\u00a0general purpose microprocessor with specific\u00a0paralleled architecture for speeding operations such\u00a0as filtering.<\/p>\n In comparison to analog filters, digital filters have\u00a0simplified designs as they are not subject to the\u00a0component non-linearities. Analog filters have\u00a0imperfect electronic components having specified\u00a0limit tolerances. These may also vary with\u00a0temperature and drift with time. The effect of\u00a0variable component errors is greatly increased with\u00a0increasing order and thus component count of\u00a0analog filters. Comparatively the digital filters are\u00a0more stable and predictable as the coefficient\u00a0values are stored in computer memory. Also the\u00a0digital filters can be used to obtain more complex\u00a0designs due to definite value of its coefficients.\u00a0Achieving the same complex design form analog\u00a0filters lead to higher engineering cost of designing.\u00a0Further the coefficients of digital filters can be\u00a0modified to create adaptive filters. Many techniques have been presented for the\u00a0improvement of digital filter design for transceiver\u00a0circuits by using various statistical and soft\u00a0computing algorithms. There is a need to develop a Figure 2.1<\/strong><\/p>\n Figure 2.3<\/p>\n CONCLUSION AND FUTURE SCOPE<\/strong><\/p>\n The Filter performance is better compared to\u00a0previous researches in the sense of much improved\u00a0and stable response and less time consumption in\u00a0its designing. The versatility of the designed filter\u00a0lies in bandwidth programmability over a wide\u00a0frequency domain\u00a0Further the work can be extended by creating a test\u00a0bed having direct interface between the matlab\u00a0simulation environment and FPGA integrated\u00a0development environment to design digital filters [11] D”Andrea, A.N.; Guglielmi, F.; Mengali,\u00a0U.; Spalvieri, A., “Design of transmit and receive\u00a0digital filters for data communications,”\u00a0Communications, IEEE Transactions on , vol.42,\u00a0no.234, pp.357,359, Feb\/Mar\/Apr 1994.<\/p>\n \n","protected":false},"excerpt":{"rendered":" pp. 13-16 Pooja Mehra1, R. P. Gupta2, Savita Shivani1 and Naveen Hemrajani3 1 Suresh Gyan Vihar University, Jaipur 2 Manda Institute of Technology, Bikaner 3 Jaipur Engineering College & Research Centre, Jaipur *Corresponding Author – reserachpaper26@gmail.com ABSTRACT This paper presents the design of programmable digital filter for transreceiver circuits. The designed filter covers a wide […]<\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[18,41],"tags":[],"class_list":["post-508","post","type-post","status-publish","format-standard","hentry","category-journal-of-environment-science-and-technology","category-volume-2-issue-1-2016-journal-of-environment-science-and-technology"],"yoast_head":"\n
\nThere has been rapid growth in communication\u00a0technologies in recent years. The mobile\u00a0communication technology development\u00a0experiences 4 stages. The first stage was from the\u00a01920 s and 40 s where mobile communication is\u00a0mainly used on ships, planes and cars, military\u00a0communication system. Second stage was from the\u00a01940 s to the 60s with the emerging of mobile\u00a0phone systems. It mainly used 150 MHz VHF\u00a0frequency band which further extended to 400\u00a0MHz band. The third stage was from the 1970 s to\u00a0the 80s, where the concept of cellular was\u00a0introduced with the use of 800 to 900 MHz band. Stage 4 extended from the 1990 s to the present\u00a0day, with the introduction of digital transmission,\u00a0CDMA, TDMA technology [1, 7].<\/p>\n
\nBACKGROUND<\/strong>
\nWei-Kang et al have designed an optimal pulseshaping\u00a0filter design for multilevel QAM\/QPR\u00a0digital radio systems. The design starts with the\u00a0receiver filter with a magnitude optimized to a\u00a0square-root. Nyquist shaping minimizes the\u00a0adjacent channel interference, the AWGN channel\u00a0BER. The radio test results are presented and\u00a0discussed [2]. Parent et al have designed a low\u00a0power and high speed 10 GHz sampling rate digital\u00a0FIR filters with powers-of-two coefficients and the\u00a0designed filter has applications in wireless\u00a0communication in digital radio transmitter. Deep\u00a0sub-micron CMOS technologies and later\u00a0nanometer scale CMOS have enabled the\u00a0development of highly digital radios for wireless\u00a0communications. [3].Clarkson et al have worked on\u00a0digital FIR filter design for spread-spectrum\u00a0receivers with reduced inherent latency. The use of\u00a0a programmable digital signal processor is\u00a0compared to a solution which uses discrete\u00a0components. Adjacent and center channel\u00a0amplitudes are programmable and are programmed\u00a0to change every hop period and in both amplitude\u00a0and envelope [4].\u00a0Grati\u00a0\u00a0et al have worked on design
\nand hardware implementation of digital channel\u00a0selection decimating filter for multistandard\u00a0receiver. This paper presents a low-power design\u00a0and an area-efficient FPGA implementation of\u00a0designed filter. Later the design was evaluated in\u00a0performance and complexity along with its support\u00a0for GSM, DECT and UMTS standard [5]. Clarkson\u00a0et al have reviewed digital filter design for\u00a0frequency-hopping receivers. A direct-synthesis\u00a0frequency synthesiser has been built which\u00a0simulates the IF signal expected in the frequency-hopping\u00a0radio. Even high-order filters may be\u00a0designed using this technique [6].<\/p>\n
\ntest bed for enabling application specific evaluation\u00a0of digital filter design for software radio. Presently\u00a0most of the work done has been either in the area of\u00a0simulation using matlab or development of\u00a0algorithms using Xilinx and other FPGA\u00a0workstations. There is a need to bridge the gap\u00a0between these two design methodologies
\nMETHODOLOGY<\/strong>
\nMATLAB is used to design Digital Filters for\u00a0Noise Cancellation in transceivers signal\u00a0conditioning. Coding in matlab will enable VHDL\u00a0interface to directly generate the vhdl code for\u00a0implementation. In this paper a programmable band\u00a0select filter is proposed which covers an entire\u00a0range of 10Mhz-40Mhz and it can be increased\u00a0beyond this range also.
\nRESULTS<\/strong>
\nA programmable band pass filter is designed in\u00a0MATLAB whose results are discussed here.\u00a0The Input and filtered output for 10 MHz-40 MHz\u00a0digital filter are shown in fig1.1-1.4.The magnitude\u00a0responses are further shown in fig.2.1-2.4<\/p>\n![\"\"](\"http:\/\/www.gyanvihar.org\/journals\/wp-content\/uploads\/2018\/12\/1-2.jpg\")
<\/p>\n![\"\"](\"http:\/\/www.gyanvihar.org\/journals\/wp-content\/uploads\/2018\/12\/1-3.jpg\")
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<\/p>\n
\nfor transceiver circuits and further analysing its\u00a0performance. Xilinx IDE will be used to construct\u00a0the VHDL code for Digital Filters for Noise\u00a0Cancellation in Transceiver Systems.
\nREFERENCES<\/strong>:
\n[1] PengLin etc. The third generation mobile\u00a0communication technology [M]. The first edition.\u00a0Beijing: electronic industry press, 2003.8 ~ 12.
\n[2] Wei-Kang Cheng; Sung-Moon Yang; Jeff\u00a0Jiao, “An optimal pulse-shaping filter design for\u00a0multilevel QAM\/QPR digital radio systems,”\u00a0Communication Technology Proceedings, 1996.\u00a0ICCT’96., 1996 International Conference on , vol.2,\u00a0no., pp.1029,1032 vol.2, 5-7 May 1996
\n[3] Parent, B.; Muller, J.; Kaiser, A.; Cathelin,\u00a0A., “Design of 10 GHz sampling rate digital FIR\u00a0filters with powers-of-two coefficients,” Circuit\u00a0Theory and Design (ECCTD), 2011 20th European\u00a0Conference on , vol., no., pp.584,587, 29-31 Aug.\u00a02011
\n[4] Clarkson, T.G.; Tsui, T. S D, “Digital\u00a0filter design for spread-spectrum receivers,”\u00a0Computer and Communication Systems, 1990.\u00a0IEEE TENCON’90., 1990 IEEE Region 10\u00a0Conference on , vol., no., pp.186,189 vol.1, 24-27\u00a0Sep 1990
\n[5] Grati, K.; Ghazel, A.; Naviner, L.,\u00a0“Design and hardware implementation of digital\u00a0channel selection decimating filter for\u00a0multistandard receiver,” Electronics, Circuits and\u00a0Systems, 2005. ICECS 2005. 12th IEEE\u00a0International Conference on , vol., no., pp.1,4, 11-14 Dec. 2005
\n[6] Clarkson, T.G.; Tsui, T. S D, “Digital\u00a0filter design for frequency-hopping receivers,”Circuits and Systems, 1990., Proceedings of the\u00a033rd Midwest Symposium on , vol., no., pp.441,444 vol.1, 12-14 Aug 1990
\n[7] Zhang Ke; Zhu Qiping; Wu YunFeng,\u00a0“The Design of Selecting Broad Band Signal\u00a0Frequency Based on the FIR Digital Filters,”\u00a0Control Engineering and Communication\u00a0Technology (ICCECT), 2012 International\u00a0Conference on , vol., no., pp.96,99, 7-9 Dec. 2012
\n[8] White, B.A.; Elmasry, M.I., “Low-power\u00a0design of decimation filters for a digital IF\u00a0receiver,” Very Large Scale Integration (VLSI)\u00a0Systems, IEEE Transactions on , vol.8, no.3,\u00a0pp.339,345, June 2000
\n[9] Signell, S.R.; Kouyoumdjiev, T.G.;\u00a0Mossberg, K.H.; Harnefors, C.G.L., “Design and\u00a0analysis of bilinear digital ladder filters,” Circuits\u00a0and Systems I: Fundamental Theory and\u00a0Applications, IEEE Transactions on , vol.43, no.2,
\npp.69,81, Feb 1996
\n[10] Grati, K.; Ghazel, A.; Naviner, L.,\u00a0“Design and hardware implementation of digital\u00a0channel selection decimating filter for\u00a0\u00a0multistandard receiver,” Electronics, Circuits and\u00a0Systems, 2005. ICECS 2005. 12th IEEE\u00a0International Conference on , vol., no., pp.1,4, 11-14 Dec. 2005<\/p>\n